Name
Abstract | ||
|---|---|---|
Real-time systems are required to respond to their physical environment within predictable time. While multi-core platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. For parallel applications with data shared across multiple cores, overhead to maintain data coherence is a major cause of execution time variability. This source of variability can be eliminated by application level control for limiting data caching at different levels of the cache hierarchy. This removes the requirement of explicit coherence machinery for selected data. We show that such control can reduce the worst case write request latency on shared data by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/MECO49872.2020.9134262 | 2020 9th Mediterranean Conference on Embedded Computing (MECO) |
Keywords | DocType | ISSN |
hardware/software co-design,worst-case execution time,cache coherence,memory contention | Conference | 2377-5475 |
ISBN | Citations | PageRank |
978-1-7281-6949-1 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ayoosh Bansal | 1 | 0 | 0.34 |
| Jayati Singh | 2 | 0 | 0.34 |
| Yifan Hao | 3 | 11 | 2.24 |
| Jen-Yang Wen | 4 | 0 | 0.34 |
| Renato Mancuso | 5 | 173 | 13.27 |
| Marco Caccamo | 6 | 425 | 31.84 |