Paper Info
Title
Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection
Abstract
This work implements a digital signal processing (DSP) accelerator for ECG signal classification. Targeting the integration into wearable devices for 24/7 monitoring, low energy consumption per classification is a key requirement, while maintaining a high classification accuracy at the same time. Co-optimization on algorithm and hardware level led to an architecture consisting mostly of convolution operations in the processing pipeline. The realized discrete wavelet transform and convolutional neural network (CNN) is utilized for continuous time-sequence classification in a sliding-window approach moving away from sample/batch-based processing typical for CNNs. In contrast to previous hardware realizations in this domain, the proposed design was validated using the benchmark dataset from the demanding CinC challenge 2017. The architecture achieves a competitive 0.781 Fl-score with only 5597 trainable parameters reducing the computational complexity of state-of-the-art ECGDNN software solutions by three orders of magnitude. Synthesis in a 22-nm FDSOI-CMOS technology features 0.783 $\mu$J per solution meeting requirements for edge device operation at high-end classification performance.
Year
DOI
Venue
2020
10.1109/ASAP49362.2020.00042
2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Keywords
DocType
ISSN
electrocardiogram (ECG) classification,low energy per solution,digital signal processing (DSP),application specific integrated circuit (ASIC),discrete wavelet transform (DWT),1D convolutional neural networks (CNN)
Conference
2160-0511
ISBN
Citations 
PageRank 
978-1-7281-7279-8
2
0.37
References 
Authors
7
3
Name
Order
Citations
PageRank
Johnson Loh120.37
Jianan Wen220.37
Tobias Gemmeke3496.49