Name
Abstract | ||
|---|---|---|
Editor’s note: This article describes a correct by construction approach to synthesize electrically and designs compliant design. By taking advantage of layout hierarchies they are able to apply this to an interesting class of circuits. — Sherief Reda, Brown University — Leon Stock, IBM — Pierre-Emmanuel Gaillardon, University of Utah |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/MDAT.2020.3042177 | IEEE Design & Test |
Keywords | DocType | Volume |
Layout,Transistors,Generators,FinFETs,Analog circuits,Routing,Annotations | Journal | 38 |
Issue | ISSN | Citations |
2 | 2168-2356 | 3 |
PageRank | References | Authors |
0.38 | 0 | 14 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tonmoy Dhar | 1 | 7 | 3.18 |
| Kishor Kunal | 2 | 9 | 3.59 |
| Yaguang Li | 3 | 11 | 3.86 |
| Meghna Madhusudan | 4 | 14 | 5.62 |
| Jitesh Poojary | 5 | 7 | 3.86 |
| Arvind Sharma | 6 | 15 | 6.01 |
| Wenbin Xu | 7 | 23 | 7.96 |
| Steven M. Burns | 8 | 563 | 104.03 |
| Ramesh Harjani | 9 | 242 | 52.65 |
| Jiang Hu | 10 | 668 | 65.67 |
| Desmond A. Kirkpatrick | 11 | 231 | 22.96 |
| Parijat Mukherjee | 12 | 3 | 2.07 |
| Sachin Sapatnekar | 13 | 4074 | 361.60 |
| Soner Yaldiz | 14 | 69 | 7.29 |