Name
Abstract | ||
|---|---|---|
Logic locking is a method to prevent intellectual property (IP) piracy. However, under a reasonable attack model, SAT-based methods have proven to be powerful in obtaining the secret key. In response, many locking techniques have been developed to specifically resist this form of attack. In this paper, we demonstrate two SAT modeling techniques that can provide many orders of magnitude speed up in discovering the correct key. Specifically, we consider relaxed encodings and symmetry breaking. To demonstrate their impact, we model and attack a state-of-the-art logic locking technique, Full-Lock. We show that circuits previously unbreakable within 15 days of run time can be solved in seconds. Consequently, in assessing the strength of any given locking, it is imperative that these modeling techniques be considered. To remedy this vulnerability in the considered locking technique, we demonstrate an extended version, logic-enhanced Banyan locking, that is resistant to our proposed modeling techniques. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1145/3400302.3415668 | 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD) |
Keywords | DocType | ISSN |
logic locking,intellectual property piracy,reasonable attack model,SAT-based methods,secret key,locking techniques,SAT modeling techniques,correct key,state-of-the-art logic,Full-Lock,given locking,considered locking technique,logic-enhanced Banyan locking,time 15.0 d | Conference | 1933-7760 |
Citations | PageRank | References |
3 | 0.38 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joseph Sweeney | 1 | 3 | 0.38 |
| Marijn J. H. Heule | 2 | 3 | 1.39 |
| Lawrence Pileggi | 3 | 358 | 31.47 |