Paper Info
Title
A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs
Abstract
The SRAM-based field-programmable gate array (FPGA) is extremely susceptible to single event upsets (SEUs) on configuration memory which can lead to soft error and malfunction of the circuit. Facing the ever-growing number of configuration bits in modern FPGAs, traditional scrubbing is getting harder to find errors in time, resulting in mismatching between the SEU sensitivity and scrubbing performance. This article proposes a hierarchical scrubbing technique that makes full use of the SEU sensitivity based on the adaptive mean time to detect (MTTD) for each frame. It distinguishes the configuration frames with multipriority and uses different scrubbing methods for different priorities. Also, a model has been built for solving the MTTD allocating problem and enabling an effective scrubbing when SEU occurrence. Moreover, the corresponding hardware architecture is supported and the fault injection-based evaluation on a Xilinx Kintex-7 FPGA is done. The result shows that it can improve mean upsets to failure from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.56 \times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$146.93 \times $ </tex-math></inline-formula> , which is proportional to the mean time to failure (MTTF) improvement.
Year
DOI
Venue
2020
10.1109/TVLSI.2020.3010647
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
DocType
Volume
Sensitivity,Single event upsets,Field programmable gate arrays,Circuit faults,Hardware,Redundancy,Maintenance engineering
Journal
28
Issue
ISSN
Citations 
10
1063-8210
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Guanghui He103.04
Sijie Zheng200.34
Naifeng Jing315227.07