Name
Abstract | ||
|---|---|---|
The support for the heterogeneous memory in the conventional virtual memory has an inherent problem. For the efficient translation in the critical translation lookaside buffers (TLBs), the page size has been growing. However, the heterogeneous memory management requires a nimble fine-grained migration mechanism to quickly move necessary memory portions to the precious fast memory.To address the challenges posed by the conflicting goals in the heterogeneous memory support, this paper proposes to decouple the address translation into a two-step process. The decoupling resolves the conflict as the critical core-side TLBs perform the translation to an intermediate address space, and the memory-side translation provides the actual physical location of the memory devices.
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Year | DOI | Venue |
|---|---|---|
2020 | 10.1145/3410463.3414662 | PACT '20: International Conference on Parallel Architectures and Compilation Techniques
Virtual Event
GA
USA
October, 2020 |
DocType | ISBN | Citations |
Conference | 978-1-4503-8075-1 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bokyeong Kim | 1 | 0 | 0.34 |
| Soojin Hwang | 2 | 0 | 0.34 |
| Sanghoon Cha | 3 | 58 | 3.63 |
| Chang Hyun Park | 4 | 0 | 0.34 |
| Jongse Park | 5 | 303 | 12.47 |
| Jaehyuk Huh | 6 | 33 | 6.28 |