Name
Abstract | ||
|---|---|---|
Scratchpad Memory (SPM) is widely used in emerging domain-specific architectures and accelerators for improving energy efficiency and time predictability. Typically, SPM-based architectures use DMA for fetching data from off-chip memory and global load instructions for loading fine-grained data directly into registers. For such architectures, neither capacity-only nor bandwidth-only loop tiling can efficiently use the bandwidth and SPM. This paper introduces a bandwidth-aware loop tiling approach that enables a tradeoff between SPM space utilization and bandwidth utilization to be made, by leveraging a runtime tiling framework and a cross-host-kernel IPA. Experimental results demonstrate that our approach can achieve the performance improvement of up to 4x, with a geometric average of 26%.
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Year | DOI | Venue |
|---|---|---|
2020 | 10.1145/3410463.3414637 | PACT '20: International Conference on Parallel Architectures and Compilation Techniques
Virtual Event
GA
USA
October, 2020 |
DocType | ISBN | Citations |
Conference | 978-1-4503-8075-1 | 1 |
PageRank | References | Authors |
0.38 | 0 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mingchuan Wu | 1 | 1 | 0.38 |
| Ying Liu | 2 | 5 | 3.55 |
| Huimin Cui | 3 | 1 | 0.38 |
| Qingfu Wei | 4 | 1 | 0.38 |
| Quanfeng Li | 5 | 1 | 0.38 |
| Limin Li | 6 | 1 | 0.38 |
| Fang Lv | 7 | 16 | 3.65 |
| Jingling Xue | 8 | 1627 | 124.20 |
| Xiaobing Feng | 9 | 906 | 112.55 |