Name
Abstract | ||
|---|---|---|
A critical component of high-throughput processors such as GPGPUs is the network-on-chip (NoC) that interconnects the cores and the memory partitions together. Different NoC architectures for throughput processors have been proposed but they have often been based on similar principles as multicore (or CPU) NoC, including emphasis on bisection bandwidth and the traffic pattern. In this work, we identify how such prior approaches are not necessarily applicable to NoC in throughput processor. We identify how different bandwidth bottleneck can be created in high-throughput processors and NoC design for throughput processors need to be re-evaluated.
|
Year | DOI | Venue |
|---|---|---|
2020 | 10.1145/3410463.3414673 | PACT '20: International Conference on Parallel Architectures and Compilation Techniques
Virtual Event
GA
USA
October, 2020 |
DocType | ISBN | Citations |
Conference | 978-1-4503-8075-1 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiho Kim | 1 | 57 | 15.00 |
| Sanghun Cho | 2 | 0 | 0.34 |
| Minsoo Rhu | 3 | 0 | 0.34 |
| Ali Bakhoda | 4 | 0 | 0.34 |
| Tor M. Aamodt | 5 | 1583 | 71.91 |
| john kim | 6 | 1412 | 72.87 |