Name
Abstract | ||
|---|---|---|
Predictable execution models have been proposed over the years to achieve contention-free execution of real-time tasks by preloading data into dedicated local memories. In this way, memory access delays can be hidden by delegating a DMA engine to perform memory transfers in parallel with processor execution. Nevertheless, state-of-the-art protocols introduce additional blocking due to priority inversion, which may severely penalize latency-sensitive applications and even worsen the system schedulability with respect to the use of classical scheduling schemes. This paper proposes a new protocol that allows hiding memory transfer delays while reducing priority inversion, thus favoring the schedulability of latency-sensitive tasks. The corresponding analysis is formulated as an optimization problem. Experimental results show the advantages of the proposed protocol against state-of-the-art solutions. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/DAC18072.2020.9218640 | 2020 57th ACM/IEEE Design Automation Conference (DAC) |
DocType | ISSN | ISBN |
Conference | 0738-100X | 978-1-7281-1085-1 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniel Casini | 1 | 26 | 6.28 |
| Paolo Pazzaglia | 2 | 2 | 2.07 |
| Alessandro Biondi | 3 | 25 | 3.33 |
| Marco Di Natale | 4 | 1237 | 91.62 |
| giorgio buttazzo | 5 | 543 | 39.95 |