Paper Info
Title
GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design
Abstract
We present the first FFE SST TX layout generator enhanced by various software techniques including a GUI-based template engine. Seven different DRC/LVS-clean TXs were generated in multiple technologies (40nm/65nm/90nm CMOS) for the first time, and achieved adequate maximum data rates: 36Gb/s with 40nm in post-layout simulation; 14Gb/s with 65nm in measurement. Total generation time was less than 5 days, including iterative parameter tuning by a human designer and computation (30 minutes for TX core, 8 hours for power network). Fast post-layout analysis of TX’s performance-power trade-off was enabled by the presented generator for the first time.
Year
DOI
Venue
2020
10.1109/DAC18072.2020.9218723
2020 57th ACM/IEEE Design Automation Conference (DAC)
Keywords
DocType
ISBN
a high-speed serial link,feed-forward equalization,source-series termination transmitter,analog layout generation
Conference
978-1-7281-1085-1
Citations 
PageRank 
References 
0
0.34
0
Authors
5
Name
Order
Citations
PageRank
seungho han121.41
Sungyu Jeong200.34
Chanho Kim3835.57
Hong-june Park446572.93
Byungsub Kim5163.60