Name
Title | ||
|---|---|---|
Towards IP integration on SoC: a case study of high-throughput and low-cost wrapper design on a novel IBUS architecture |
Abstract | ||
|---|---|---|
To integrate third-party intellectual properties (IPs) into a new system-on-chip (SoC) architecture is a big challenge. Therefore, this study first presents a new bus protocol named as integrated bus (IBUS), and more important, a configurable bus wrapper for connecting AXI3-interfaced IPs into IBUS is further proposed, aiming to finding the optimal balance between bus efficiency and resource cost in terms of field-programming gate array slice count, bus transfer latency, and energy consumption. As a case study, the authors implemented three IBUS wrappers for integrating three AXI3-interfaced verification IPs into an IBUS SoC. Experimental results show that their proposed work achieves a higher valid data throughput (
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in the block test and
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in the cipher test) compared with the designs on conventional bridge-based SoC integration, as well as a large reduction in the normalised slice-time-power (18.73% in the block benchmark and 23.45% in the cipher benchmark) when setting the same weights of slice number, data transfer latency, and energy dissipation. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1049/iet-cdt.2019.0090 | IET Computers & Digital Techniques |
Keywords | DocType | Volume |
system-on-chip,industrial property,field programmable gate arrays,logic design,cryptographic protocols | Journal | 14 |
Issue | ISSN | Citations |
6 | 1751-8601 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaokun Yang | 1 | 14 | 6.15 |
| Shi Sha | 2 | 0 | 0.34 |
| Ishaq Unwala | 3 | 0 | 0.34 |
| Lu Jiang | 4 | 4 | 1.79 |