Name
Abstract | ||
|---|---|---|
This article proposes an automatic compiler for an on-chip time-to-digital converter (TDC) that can be used for monitoring the on-chip operating conditions such as temperature and supply voltage. The proposed compiler adopts a resilient architecture and supports self-calibration and range adjustment. In addition, a novel technique for fine-shrinking cell analysis is proposed to explore the tradeoffs among area, timing resolution, operating range, etc. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/MDAT.2020.2991676 | IEEE Design & Test |
Keywords | DocType | Volume |
Time-to-Digital Converter,TDC Compiler,Pulse-Shrinking,Fine-Shrinking Cell Analysis | Journal | 37 |
Issue | ISSN | Citations |
4 | 2168-2356 | 1 |
PageRank | References | Authors |
0.36 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chia-Hua Wu | 1 | 2 | 2.41 |
| Shi-Yu Huang | 2 | 766 | 70.53 |
| Yung-Fa Chou | 3 | 10 | 2.26 |
| Ding-Ming Kwai | 4 | 521 | 46.85 |