Name
Abstract | ||
|---|---|---|
We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (-1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TCSI.2020.2990748 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | DocType | Volume |
Multi-valued logic,ternary logic circuits,logic synthesis methodology,body effect,CNTFETs | Journal | 67 |
Issue | ISSN | Citations |
9 | 1549-8328 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sunmean Kim | 1 | 1 | 2.37 |
| Yun-Sung Lee | 2 | 14 | 2.83 |
| Sunghye Park | 3 | 0 | 0.34 |
| Kyung Rok Kim | 4 | 6 | 2.33 |
| Seokhyeong Kang | 5 | 388 | 32.89 |