Name
Abstract | ||
|---|---|---|
In recent years, dedicated hardware accelerators for the acceleration of the convolutional neural network (CNN) have been extensively studied. Although many studies have presented efficient designs on FPGAs for image classification neural network models such as AlexNet and VGG, there are still little implementations for CNN-based object detection applications. This paper presents an OpenCL-based high-throughput FPGA accelerator for the YOLOv2 object detection algorithm on Arria-10 GX1150 FPGA. The proposed hardware architecture adopts a scalable pipeline design to support multi-resolution input image and full 8-bit fixed-point datapath to improve hardware resource utilization. Layer fusion technology that merges the convolution, batch normalization and Leaky-ReLU is also developed to avoid transmission of intermediate data between FPGA and external memory. Experimental results show that the final design achieves a peak throughput of 566 GOP/s under the working frequency of 190 MHz. The accelerator can execute YOLOv2 inference computation (288x288 resolution) and tiny YOLOv2 (416x416resolution) at the speed of 35 and 71 FPS, respectively. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1007/s11554-020-00977-w | JOURNAL OF REAL-TIME IMAGE PROCESSING |
Keywords | DocType | Volume |
Hardware accelerator, FPGA, Convolutional neural network, Object detection, YOLOv2 | Journal | 18 |
Issue | ISSN | Citations |
3 | 1861-8200 | 1 |
PageRank | References | Authors |
0.37 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ke Xu | 1 | 1 | 0.70 |
| Xiaoyun Wang | 2 | 2338 | 170.86 |
| Xinyang Liu | 3 | 1 | 0.37 |
| Changfeng Cao | 4 | 1 | 0.37 |
| Huolin Li | 5 | 1 | 0.37 |
| Haiyong Peng | 6 | 1 | 0.37 |
| Dong Wang | 7 | 1351 | 186.07 |