Paper Info
Title
READY: Reliability- and Deadline-Aware Power-Budgeting for Heterogeneous Multicore Systems
Abstract
Tackling the dark silicon problem in a heterogeneous multicore system, the temperature constraints across the system should be addressed carefully by assigning a proper set of tasks to a pool of the heterogeneous cores during the run-time. When such a system is utilized in a reliable/real-time application, the reliability/timing constraints of the application should also be augmented to the temperature constraints and make the tasks mapping problem more and more complex. To solve the mapping problem in such a situation, we propose READY; an online reliability- and deadline-aware mapping and scheduling algorithm for heterogeneous multicore systems. READY utilizes an adaptive power constraint (as a metric for temperature measurement) that is updated according to the number and position of the active cores on the chip. READY, first, attempts to meet the reliability target of the system by improving the reliability of each task. Then, it performs the mapping and scheduling of the tasks on cores of different islands, so that the peak power and timing constraints are met. The simulation results illustrate that while READY guarantees the timing constraints and meets reliability targets, it improves the peak-power-aware system schedulability (chip performance) by 23.77% (up to 40.69%).
Year
DOI
Venue
2021
10.1109/TCAD.2020.3003288
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
DocType
Volume
Heterogeneous architectures,power constraint,reliability,schedulability,timing constraint
Journal
40
Issue
ISSN
Citations 
4
0278-0070
1
PageRank 
References 
Authors
0.35
0
6
Name
Order
Citations
PageRank
Javad Saber-Latibari121.38
Mohsen Ansari2112.88
Pourya Gohari-Nazari310.69
Sina Yari-Karin420.71
Amir Mahdi Hosseini Monazzah5326.89
Alireza Ejlali643338.60