Name
Abstract | ||
|---|---|---|
This paper presents the debug process of a 28 GHz low noise amplifier (LNA) circuit layout. This study is guided utilizing an electromagnetic (EM) simulation program where inductive coupling, the parasitics of dc voltage line and ground line are extracted and simulated, their impacts on LNA performance are also quantitatively characterized. For validation, the circuit was designed and fabricated using GF8HP 0.13 um SiGe BiCMOS process. The measurement shows that the gain S21 is 23.22 dB, S11 and S22 are -18 and -26 dB, respectively, and the noise figure is 4.26 dB. The power consumption is 14.25 mW, the chip area including pads is 540 um x810 um. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1142/S021812662050262X | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Keywords | DocType | Volume |
LNA, Ka band, diagnosis, layout modification, electromagnetic simulations | Journal | 29 |
Issue | ISSN | Citations |
16 | 0218-1266 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wenzhe Chen | 1 | 0 | 0.34 |
| Jaifei Yao | 2 | 0 | 0.34 |
| Tian Xia | 3 | 39 | 5.50 |