Title
On-Chip Error-Triggered Learning of Multi-Layer Memristive Spiking Neural Networks
Abstract
Recent breakthroughs in neuromorphic computing show that local forms of gradient descent learning are compatible with Spiking Neural Networks (SNNs) and synaptic plasticity. Although SNNs can be scalably implemented using neuromorphic VLSI, an architecture that can learn using gradient-descent in situ is still missing. In this paper, we propose a local, gradient-based, error-triggered learning algorithm with online ternary weight updates. The proposed algorithm enables online training of multi-layer SNNs with memristive neuromorphic hardware showing a small loss in the performance compared with the state-of-the-art. We also propose a hardware architecture based on memristive crossbar arrays to perform the required vector-matrix multiplications. The necessary peripheral circuitry including presynaptic, post-synaptic and write circuits required for online training, have been designed in the subthreshold regime for power saving with a standard 180 nm CMOS process.
Year
DOI
Venue
2020
10.1109/JETCAS.2020.3040248
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Keywords
DocType
Volume
On-chip learning,surrogate gradient (SG) learning,Spiking Neural Networks (SNNs),memristive devices
Journal
10
Issue
ISSN
Citations 
4
2156-3357
2
PageRank 
References 
Authors
0.38
0
5
Name
Order
Citations
PageRank
Melika Payvand1223.20
Mohamed E. Fouda23118.55
Fadi J. Kurdahi31113124.67
Ahmed M. Eltawil483484.43
Emre Neftci518317.52