Abstract | ||
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This paper presents a compact DAC for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET CMOS, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad switched capacitors. The 14 GS/s 8-bit design occupies only 0.011 mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
and supports up to 0.32 V
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signal swing across its differential 100 Ω load. It achieves IM3 <; -45.3 dBc across the first Nyquist zone while consuming 50 mW from a single 0.8 V supply. |
Year | DOI | Venue |
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2020 | 10.1109/VLSICircuits18222.2020.9162776 | 2020 IEEE Symposium on VLSI Circuits |
Keywords | DocType | ISSN |
digital-to-analog converter,transmitter,switched-capacitor circuits | Conference | 2158-5601 |
ISBN | Citations | PageRank |
978-1-7281-9943-6 | 0 | 0.34 |
References | Authors | |
2 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
Pietro Caragiulo | 1 | 2 | 1.13 |
Oscar Elisio Mattia | 2 | 2 | 0.79 |
amin arbabian | 3 | 227 | 35.52 |
Boris Murmann | 4 | 594 | 82.64 |