Name
Abstract | ||
|---|---|---|
In the physical design of VLSI circuits, the congestion generated in placement stage tends to enlarge the total wirelength (TWL) and further worsens the timing and routability. In this letter, a local congestion elimination technique is proposed which can be compatible with available commercial P&R EDA tools. Driven by overflow value, the optimal keep-out margins being added around the highest pin cells in specific congestion regions are searched using simulated annealing (SA) algorithm and ant colony optimization (ACO) algorithm respectively to ameliorate local congestion. Experimental results have shown that the proposed technique can reduce the design rule violations (DRV), shorts and TWL significantly. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1587/elex.17.20200232 | IEICE ELECTRONICS EXPRESS |
Keywords | DocType | Volume |
design automation, physical design, placement, congestion, overflow, heuristic algorithm | Journal | 17 |
Issue | ISSN | Citations |
17 | 1349-2543 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| W. Wu | 1 | 105 | 27.20 |
| Zhixiong Di | 2 | 2 | 3.09 |
| Jiangyi Shi | 3 | 4 | 2.49 |
| Quanyuan Feng | 4 | 147 | 25.34 |
| Zhengguang Tang | 5 | 0 | 0.68 |