Abstract | ||
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Polar codes are one of the most favorable capacity-achieving codes owing to their simple structures and low decoding complexity. Successive cancellation list (SCL) decoders with large list sizes achieve performances very close to those of maximum-likelihood (ML) decoders. However, hardware cost is a severe problem because an SCL decoder with list size L consists of L copies of a successive cancellation (SC) decoder. To address this issue, a stochastic SCL (SSCL) polar decoder is proposed. Although stochastic computing can achieve a good hardware reduction compared with the deterministic one, its straightforward application to an SCL decoder is not well-suited owing to the precision loss and severe latency. Therefore, a doubling probability approach and adaptive distributed sorting (DS) are introduced. A corresponding hardware architecture is also developed. Field programmable gate array (FPGA) results demonstrate that the proposed stochastic SCL polar decoder can achieve a good performance and complexity tradeoff. |
Year | DOI | Venue |
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2020 | 10.1007/s11432-019-2924-6 | SCIENCE CHINA-INFORMATION SCIENCES |
Keywords | DocType | Volume |
SCL polar decoder,stochastic computing,2-bit decoding,distributed sorting,hardware | Journal | 63 |
Issue | ISSN | Citations |
10 | 1674-733X | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
---|---|---|---|
Xiao Liang | 1 | 44 | 10.89 |
Huizheng Wang | 2 | 0 | 0.34 |
Yifei Shen | 3 | 15 | 5.36 |
Zaichen Zhang | 4 | 134 | 20.67 |
xiaohu you | 5 | 2529 | 272.49 |
Chuan Zhang | 6 | 100 | 13.67 |