Name
Title | ||
|---|---|---|
Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs |
Abstract | ||
|---|---|---|
The fully connected 3D-NoCs in which all routers are vertically connected with their neighbors above and below need a lot of Through-Silicon-Vias (TSVs), and they will occupy a large silicon area and reduce the fabrication yield. Thus, the idea of partially connected 3D-NoCs has emerged. The optimal number and placement of the vertical links (elevators) must be determined at the chip design stage,... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TCAD.2020.3038338 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Elevators,Three-dimensional displays,Through-silicon vias,Optimization,Genetic algorithms,Routing,Silicon | Journal | 40 |
Issue | ISSN | Citations |
10 | 0278-0070 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuxiang Fu | 1 | 11 | 5.65 |
| Chuan Zhang | 2 | 100 | 13.67 |
| Wenqing Song | 3 | 15 | 3.35 |
| Qinyu Chen | 4 | 57 | 5.87 |
| Hui Chen | 5 | 3 | 1.76 |
| Minghao Zhou | 6 | 11 | 1.45 |
| Li Li | 7 | 25 | 8.15 |