Name
Title | ||
|---|---|---|
Design And Analysis Of Improved High-Speed Adaptive Filter Architectures For Ecg Signal Denoising |
Abstract | ||
|---|---|---|
In this paper, improved high-speed adaptive filter-based denoising architectures are proposed and implemented using the Xilinx Virtex-6 series FPGA platform. The performance of the proposed DF-RDLMS, TDF-RDLMS and TF-RDLMS implementations is analyzed and compared with that of the existing adaptive filter architectures as well as state-of-the-art wavelet-based denoising architectures. The proposed adaptive filter implementations are found to perform better than existing adaptive filter architectures and wavelet-based architectures. As compared to the existing adaptive filter implementations, the proposed architectures facilitate design flexibility in choice of the step-size parameter and also allow processing of input signals in fixed-point format as well as floating-point format. Simulation results exhibit the effectiveness of the proposed architectures in efficiently denoising ECG signals in noisy environments and prove their high suitability for low-cost high-performance denoising applications in medical field. Moreover, it is observed that the proposed high-speed adaptive filter architectures require significantly less hardware as compared to state-of-the-art wavelet-based architectures. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1016/j.bspc.2020.102221 | BIOMEDICAL SIGNAL PROCESSING AND CONTROL |
Keywords | DocType | Volume |
FPGA, High-speed adaptive filter architecture, Wavelet transform, Wavelet packet transform, Signal denoising | Journal | 63 |
ISSN | Citations | PageRank |
1746-8094 | 1 | 0.35 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mahesh Chandra | 1 | 69 | 16.38 |
| Pankaj Goel | 2 | 1 | 0.35 |
| Ankita Anand | 3 | 2 | 1.40 |
| Asutosh Kar | 4 | 15 | 6.33 |