Name
Abstract | ||
|---|---|---|
In low-power digital circuit, the deviation of node voltage from nominal value due to charge-sharing leads to erroneous output. This problem is more prominent in domino logic when the device is scaled down. The scaling of the device involves scaling of threshold voltage, resulting in high leakage, less robustness and degradation in noise margin. The paper proposes an improved domino approach in terms of reduced leakage, low power dissipation and better noise margin. The stacking effect and pseudo buffer are used in precharge phase to control the gate-to-source voltage of pull-down network for less power consumption and increase in performance in terms of speed of operation. A modified keeper is introduced to reduce the charge-sharing problem. The proposed domino approach is tested against area overhead, ageing and process, voltage and temperature variation. The circuit is simulated using Cadence Virtuoso Spectre for 90 nm technology. The results obtained from the simulation represent the usefulness of the proposed circuit in terms of power dissipation, stability due to temperature variation, leakage due to temperature variation and delay. The result also shows that the circuit is less prone to charge redistribution problem that exist in domino circuit. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1002/cta.2798 | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
Keywords | DocType | Volume |
charge-sharing, domino logic, keeper circuit, noise immunity, UNA | Journal | 48 |
Issue | ISSN | Citations |
8 | 0098-9886 | 1 |
PageRank | References | Authors |
0.37 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sapna Rani Ghimiray | 1 | 1 | 0.71 |
| Preetisudha Meher | 2 | 1 | 0.71 |
| Pranab Kishore Dutta | 3 | 1 | 1.39 |