Name
Abstract | ||
|---|---|---|
A timer and interrupt management infrastructure is essential for a computer system executing a preemptive operating system. This holds for single- and also for multicore systems. When it comes to OS-capable ISA-heterogeneous multicore systems (systems that include cores of different ISAs, which all are capable of executing an operating system) the different timer and interrupt infrastructures of the different system ISAs are still applicable. However, if reconfigurability is added on top of the ISA heterogeneity, meaning that the composition (number of individual cores) is runtime adaptable, the timer and interrupt management infrastructure needs to be reconsidered. In this paper, a unified timer and interrupt management scheme is deduced for a runtime adaptable, OS-capable, ISA-heterogeneous multi-core system, consisting of ARM and RISC-V cores, that are capable of executing Linux. This is done by analyzing/surveying the timer and interrupt management schemes of RISC-V and ARM systems. Finally this paper will show that RISC-V timer and interrupt management devices are suitable to also manage timers and interrupts for ARM based systems. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/IECON43393.2020.9255193 | IECON 2020: THE 46TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY |
Keywords | DocType | ISSN |
heterogeneous multicore, ARM, RISC-V, timer management, interrupt management | Conference | 1553-572X |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marcel Eckert | 1 | 3 | 2.55 |
| Haase, J. | 2 | 6 | 6.13 |
| Bernd Klauer | 3 | 50 | 14.36 |