Name
Title | ||
|---|---|---|
A 4GHz 0.73ps<inf>rms</inf>-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC |
Abstract | ||
|---|---|---|
This paper proposes a fractional-N sub-sampling ring PLL employing a jitter-tracking DLL-assisted DTC. The DTC achieves 0.49ps resolution and 0.98LSB
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub>
INL with a dynamic range reduction through multi-phases of the DLL. In addition, an adaptive pulse-width control technique allows the loop BW to be insensitive to PVT, yielding <; 9.6% jitter variation. The proposed ring PLL fabricated in a 14nm FinFET CMOS process achieves 0.73ps
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ms</sub>
-integrated-jitter and 10.2mW power in fractional-N mode. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/VLSICircuits18222.2020.9162861 | 2020 IEEE Symposium on VLSI Circuits |
Keywords | DocType | ISSN |
integrated-jitter,jitter-tracking DLL-assisted DTC,jitter variation,PVT-insensitive fractional-N sub-sampling ring PLL,dynamic range reduction,adaptive pulse-width control technique,FinFET CMOS process,fractional-N mode,time 0.49 ps,size 14.0 nm,power 10.2 mW,frequency 4 GHz | Conference | 2158-5601 |
ISBN | Citations | PageRank |
978-1-7281-9943-6 | 1 | 0.35 |
References | Authors | |
0 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaehong Jung | 1 | 1 | 0.35 |
| Sangdon Jung | 2 | 2 | 1.80 |
| Kyungmin Lee | 3 | 2 | 3.09 |
| Jun-Hee Jung | 4 | 1 | 0.35 |
| Seungjin Kim | 5 | 1 | 0.35 |
| Byungki Han | 6 | 1 | 0.35 |
| Seunghyun Oh | 7 | 1 | 3.73 |
| jongwoo lee | 8 | 7 | 6.21 |