Name
Abstract | ||
|---|---|---|
This paper describes a 4 × 112 Gb/s digital receiver targeting Long Reach (LR) channels. The discrete time front-end overcomes gain-BW limitations to provide 10+dB gain at 28GHz. A 56GS/s ADC then converts the signal to 6-b digital consuming only 195mW. The following DFE-FFE based digital equalizer is capable of compensating 36 dB loss achieving BER of 2e-5. Furthermore, TDC and ISI filter based low latency timing recovery meets jitter tolerance specs over a wide range of data rates (25Gb/s NRZ to 106.25Gb/s PAM-4). The overall receiver consumes 338mW with 3.18pJ/bit energy efficiency |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/VLSICircuits18222.2020.9162802 | 2020 IEEE Symposium on VLSI Circuits |
Keywords | DocType | ISSN |
DFE-FFE,PAM-4,112 Gb/s | Conference | 2158-5601 |
ISBN | Citations | PageRank |
978-1-7281-9943-6 | 0 | 0.34 |
References | Authors | |
2 | 17 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haidang Lin | 1 | 4 | 1.84 |
| Charles Boecker | 2 | 0 | 0.34 |
| Masum Hossain | 3 | 80 | 15.83 |
| Shankar Tangirala | 4 | 0 | 0.34 |
| Roxanne Vu | 5 | 3 | 1.42 |
| Socrates D. Vamvakos | 6 | 14 | 3.62 |
| Eric Groen | 7 | 3 | 1.42 |
| Simon Li | 8 | 27 | 6.27 |
| prashant choudhary | 9 | 5 | 1.93 |
| Nanyan Wang | 10 | 3 | 1.75 |
| Masumi Shibata | 11 | 3 | 1.75 |
| Mohammad Hossein Taghavi | 12 | 4 | 2.52 |
| Marcus van Ierssel | 13 | 86 | 15.13 |
| AdilHussain Maniyar | 14 | 0 | 0.34 |
| Adam Wodkowski | 15 | 0 | 0.34 |
| Nhat Nguyen | 16 | 5 | 2.52 |
| Shaishav Desai | 17 | 11 | 3.75 |