Paper Info
Title
A 0.0046mm<sup>2</sup> 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero
Abstract
This paper presents a high-gain energy-efficient three-stage amplifier which employs buffering-based pole relocation and a dual-path structure (BPR-DP). The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth of the local feedback loop (LFL), thus improving FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> by 1.36 times, LC-FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> by 1.26 times, and LC-FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> by 3.18 times, as well as the performance robustness, compared to the state-of-the-art designs.
Year
DOI
Venue
2020
10.1109/VLSICircuits18222.2020.9162960
2020 IEEE Symposium on VLSI Circuits
Keywords
DocType
ISSN
dual-path structure,BPR-DP,unity-gain bandwidth,local feedback loop,three-stage amplifier,high-gain energy-efficient amplifier,capacitive load,buffering-based pole relocation,power 6.7 muW,capacitance 0.5 nF to 1.9 nF
Conference
2158-5601
ISBN
Citations 
PageRank 
978-1-7281-9943-6
0
0.34
References 
Authors
0
10
Name
Order
Citations
PageRank
Hongseok Shin121.48
Jinuk Kim220.81
Doojin Jang320.81
Donghee Cho400.68
Yoontae Jung511.36
Hyungjoo Cho600.68
Unbong Lee701.01
Chul Kim800.34
Sohmyung Ha97412.43
Minkyu Je1033358.17