Name
Abstract | ||
|---|---|---|
The analysis and design of a speed efficient current mode logic (CML) based new frequency divider made of cross-coupled PMOS latch based D-flipflop is discussed in this article. The realization of the proposed configuration on Cadence Virtuoso platform for 90nm CMOS process shows a wide frequency locking range as compared to the conventional current mode design counterpart and other prior arts. This work doesn't only improve the frequency range of operation, but also improvises the performance for low power applications as it consumes an average power of 2.308mW at a supply voltage of 1.2V when switches with a 10GHz clock. Also, a frequency change of 8.69GHz per mWatt power burn is noted during the estimation of figure-of-merit (FOM). |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/NorCAS51424.2020.9264995 | 2020 IEEE Nordic Circuits and Systems Conference (NorCAS) |
Keywords | DocType | ISBN |
Current mode logic,frequency divider,wide locking range,SerDes | Conference | 978-1-7281-9227-7 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Madhusudan Maiti | 1 | 0 | 0.34 |
| Shubhro Chakrabartty | 2 | 0 | 0.34 |
| Alaaddin Al-Shidaifat | 3 | 0 | 0.34 |
| hanjung | 4 | 2 | 4.57 |
| Bidyut K. Bhattacharyya | 5 | 7 | 4.94 |
| Alak Majumder | 6 | 12 | 9.29 |