Paper Info
Title
Evaluating performance of Parallel Matrix Multiplication Routine on Intel KNL and Xeon Scalable Processors
Abstract
In high-performance computing, xGEMM routine is the core of Level 3 BLAS operation to achieve matrix-matrix multiplications. The performance of Parallel xGEMM (PxGEMM) is significantly affected by two major factors: Firstly, the flop rate that can be achieved by calculating matrix-matrix multiplication on each node. Secondly, communication costs for broadcasting sub-matrices to others. In this paper, an approach to improve and adjust PDGEMM routine for modern Intel computers: Knights Landing (KNL) and Xeon Scalable Processors (SKL) is proposed. This approach consists of two methods to deal with the factors mentioned above. First, the improvement of PDGEMM for the computation part is suggested based on a blocked matrix-matrix multiplication algorithm by providing better fits for architectures of KNL and SKL to deliver a better block size computation. Second, a communication routine with MPI is proposed to overcome default settings of BLACS which is a part of communication, to improve a time-wise cost efficiency. The proposed PDGEMM achieves similar performance on smaller size matrices as PDGEMM from ScaLAPACK and Intel MKL on 16 node Intel KNL. Furthermore, the proposed PDGEMM achieves better performance (on smaller size matrices) compared to PDGEMM from ScaLAPACK and Intel MKL on 16 nodes Xeon scalable processors.
Year
DOI
Venue
2020
10.1109/ACSOS-C51401.2020.00027
2020 IEEE International Conference on Autonomic Computing and Self-Organizing Systems Companion (ACSOS-C)
Keywords
DocType
ISBN
Parallel matrix-matrix multiplication,Parallel BLAS,ScaLAPACK,Intel Knights Landing,Intel Xeon Scalable,AVX-512
Conference
978-1-7281-8415-9
Citations 
PageRank 
References 
0
0.34
0
Authors
4
Name
Order
Citations
PageRank
Thi My Tuyen Nguyen100.34
Yoosang Park200.34
Jae-Young Choi3783110.19
Raehyun Kim400.34