Paper Info
Title
A Two-Way Sram Array Based Accelerator For Deep Neural Network On-Chip Training
Abstract
On-chip training of large-scale deep neural networks (DNNs) is challenging due to computational complexity and resource limitation. Compute-in-memory (CIM) architecture exploits the analog computation inside the memory array to speed up the vector-matrix multiplication (VMM) and alleviate the memory bottleneck. However, existing CIM prototype chips, in particular, SRAM-based accelerators target at implementing low-precision inference engine only. In this work, we propose a two-way SRAM array design that could perform bi-directional in-memory VMM with minimum hardware overhead. A novel solution of signed number multiplication is also proposed to handle the negative input in backpropagation. We taped-out and validated proposed two-way SRAM array design in TSMC 28nm process. Based on the silicon measurement data on CIM macro, we explore the hardware performance for the entire architecture for DNN on-chip training. The experimental data shows that proposed accelerator can achieve energy efficiency of similar to 3.2 TOPS/W, >1000 FPS and >300 FPS for ResNet and DenseNet training on ImageNet, respectively.
Year
DOI
Venue
2020
10.1109/DAC18072.2020.9218524
PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC)
DocType
ISSN
Citations 
Conference
0738-100X
0
PageRank 
References 
Authors
0.34
0
10
Name
Order
Citations
PageRank
Hongwu Jiang1166.77
Shanshi Huang2156.75
Xiaochen Peng36112.17
Jian-Wei Su4133.61
Yen-Chi Chou582.20
Wei-Hsing Huang6252.56
Ta-Wei Liu772.83
Ruhui Liu8101.93
Meng-Fan Chang945945.63
Shimeng Yu1049056.22