Paper Info
Title
Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices
Abstract
This paper proposes a specialized coarse grained architecture for the communication functions of reconfigurable devices in globally asynchronous locally synchronous systems. Our configurable logic block includes four 40-bit data registers that can be configured as MOUSETRAP pipeline stages, and 10-15 times more look-up tables/flip-flops than the typical conventional fine grained architecture. Dedicated routing tracks for data-path signals are also prepared in our architecture. Finally, our switch boxes for data-path tracks can be configured from user circuits, enabling efficient implementation of user-controlled multiplexers. Implementation of user circuits on the proposed architecture is supported by a set of our naive mapping tools, and they were used to implement several benchmark circuits for performance comparisons between the proposed architecture and the conventional fine grained architecture. In an experimental evaluation, the throughput of communication-oriented circuits was 2-3 times higher in our architecture than in its fine grained counterpart.
Year
DOI
Venue
2020
10.1109/ASYNC49171.2020.00023
2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
Keywords
DocType
ISSN
asynchronous reconfigurable devices,specialized coarse grained architecture,communication functions,globally asynchronous locally synchronous systems,configurable logic block,data registers,MOUSETRAP pipeline stages,dedicated routing tracks,data-path signals,data-path tracks,user circuits,user-controlled multiplexers,communication-oriented circuits,conventional fine grained architecture,word length 40 bit
Conference
2643-1394
ISBN
Citations 
PageRank 
978-1-7281-5496-1
0
0.34
References 
Authors
6
2
Name
Order
Citations
PageRank
Tomohiro Yoneda135341.62
Masashi Imai2367.63