Paper Info
Title
Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance
Abstract
The overwhelming majority of High Performance Computing (HPC) systems and server infrastructure uses Intel x86 processors. This makes an architectural analysis of these processors relevant for a wide audience of administrators and performance engineers. In this paper, we describe the effects of hardware controlled energy efficiency features for the Intel Skylake-SP processor. Due to the prolonged micro-architecture cycles, which extend the previous Tick-Tock scheme by Intel, our findings will also be relevant for succeeding architectures. The findings of this paper include the following: C-state latencies increased significantly over the Haswell-EP processor generation. The mechanism that controls the uncore frequency has a latency of approximately 10ms and it is not possible to truly fix the uncore frequency to a specific level. The out-of-order throttling for workloads using 512 bit wide vectors also occurs at low processor frequencies. Data has a significant impact on processor power consumption which causes a large error in energy models relying only on instructions.
Year
DOI
Venue
2019
10.1109/HPCS48598.2019.9188239
2019 International Conference on High Performance Computing & Simulation (HPCS)
Keywords
DocType
ISBN
Microprocessors,Performance analysis,Systems modeling,Dynamic voltage scaling
Conference
978-1-7281-4485-6
Citations 
PageRank 
References 
2
0.38
0
Authors
5
Name
Order
Citations
PageRank
Robert Schöne120.38
Thomas Ilsche217214.92
Mario Bielert332.82
Andreas Gocht492.24
Daniel Hackenberg540028.07