Paper Info
Title
A 37 nW MOSFET-Only Voltage Reference in 0.13 μm CMOS
Abstract
This work presents the design of a MOS-only voltage reference with nano-watt power consumption. The proposed circuit consists of a threshold voltage monitor circuit cascaded with a high-slope proportional to absolute temperature (PTAT) voltage generator. The operation of the circuit is analytically described and a design methodology is presented. The proposed circuit was designed and simulated in a standard 130 nm CMOS process while consuming just 37 nW under 1.2 V of power supply at room temperature. Simulation results present a 585 mV reference voltage with a typical temperature coefficient (TC) of 10.13 ppm/°C, for a temperature range from -40 to 125 °C, a power supply rejection ratio (PSRR) of -54.41 dB at 100 Hz, and a line sensitivity of 0.071 %/V was found for a supply range from 1 V to 1.8 V. Monte-Carlo simulations are presented to evaluate the sensitivity to fabrication variability. The estimated silicon area is 0.0078 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
Year
DOI
Venue
2020
10.1109/SBCCI50935.2020.9189914
2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI)
Keywords
DocType
ISBN
Voltage Reference,Low Power,Threshold Voltage Extractor,MOS-only,CMOS Analog Design
Conference
978-1-7281-9626-8
Citations 
PageRank 
References 
0
0.34
14
Authors
2
Name
Order
Citations
PageRank
Vanessa F. de Lima100.68
hamilton klimach27120.07