Name
Abstract | ||
|---|---|---|
The Piccolo block cipher is a lightweight block encryption for hardware use. Hardware devices are equipped with limited computation resources and small memory. In this paper, we propose an implementation to carry out through several trade-offs between area and speed. We implemented the Piccolo block cipher algorithm with 128-bit key in two different architectures on FPGA: the iterative and the 4-bit serial architectures. The proposed implementation was performed on Xilinx Spartan-3. The iterative implementation achieves 76% of resource utilization. This implementation takes 31 clock cycles to perform the encryption or decryption. So, it results in a throughput of 151.1 Mbps. The serial implementation was optimized in terms of area to reduce the cost. It achieves 54% of resource utilization and takes 496 clock cycles resulting in a throughput of 6.39 Mbps. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ATSIP49331.2020.9231586 | 2020 5th International Conference on Advanced Technologies for Signal and Image Processing (ATSIP) |
Keywords | DocType | ISSN |
lightweight block cipher,Piccolo block cipher,FPGA,Cryptography,Hardware architectures,low area,VHDL | Conference | 2641-5941 |
ISBN | Citations | PageRank |
978-1-7281-7514-0 | 0 | 0.34 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ayoub Mhaouch | 1 | 0 | 0.34 |
| Wajdi Elhamzi | 2 | 15 | 2.89 |
| Mohamed Atri | 3 | 154 | 27.75 |