Name
Title | ||
|---|---|---|
10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture |
Abstract | ||
|---|---|---|
This article presents a multiprotocol DSP-DACbased SerDes architecture. The lookup table (LUT)-based DSP provides flexible number of taps for equalization, and soft switching driver allows 1.2-Vpp transmit swing to achieve higher SNR. The architecture employs cascaded phase-locked loop (PLL)based flexible clocking to support a wide range of data rates from 10 to 112 Gb/s. The LC PLL generates 10.25-14.5 GHz but distributes a divided version of the clock between 2.25 and 3.625 GHz with less than 140-fs integrated jitter. The local ring PLL multiplies the clock to 28 GHz but keeps the jitter less than 180 fs thanks to wide loop bandwidth. The transmitter is implemented in 7-nm FinFET consuming 175 mW with 1.56-pJ/bit efficiency. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/JSSC.2020.3036981 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
112 Gb/s,cascaded phase-locked loop (PLL),DSP-DAC,flexible clocking,high swing driver,PAM-4,PLL linear model,SerDes,sub-sampling PLL | Journal | 56 |
Issue | ISSN | Citations |
1 | 0018-9200 | 1 |
PageRank | References | Authors |
0.36 | 10 | 15 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eric Groen | 1 | 3 | 1.42 |
| Charlie Boecker | 2 | 3 | 1.08 |
| Masum Hossain | 3 | 80 | 15.83 |
| Roxanne Vu | 4 | 3 | 1.42 |
| Socrates D. Vamvakos | 5 | 14 | 3.62 |
| Haidang Lin | 6 | 4 | 1.84 |
| Simon Li | 7 | 27 | 6.27 |
| Marcus van Ierssel | 8 | 86 | 15.13 |
| prashant choudhary | 9 | 5 | 1.93 |
| Nanyan Wang | 10 | 3 | 1.75 |
| Masumi Shibata | 11 | 3 | 1.75 |
| Mohammad Hossein Taghavi | 12 | 4 | 2.52 |
| Kulwant Brar | 13 | 3 | 0.74 |
| Nhat Nguyen | 14 | 5 | 2.52 |
| Shaishav Desai | 15 | 11 | 3.75 |