Name
Title | ||
|---|---|---|
An Optimized Implementation of AES-GCM for FPGA Acceleration Using High-Level Synthesis |
Abstract | ||
|---|---|---|
Field-programmable gate array (FPGA) is growing as a new platform for accelerating heavy computational tasks such as machine learning and cryptography. To making FPGA acceleration as easy as conventional one by graphics processing units, FPGA vendors are providing high-level synthesis tools, such as Xilinx’s SDAccel, that synthesize a circuit from a program written by languages such as C, C++, and OpenCL. The benefit of high-level synthesis, however, comes with the stronger abstraction that makes optimization challenging compared to conventional development using a hardware description language, and there is only a limited publications on how to optimize the performance of a synthesized circuit. In this paper, we take the authenticated encryption algorithm AES-GCM as an example, and show the case study on how to optimize the performance: starting from a naive baseline implementation and achieving a fully pipelined implementation that accepts 128-bit message block every cycle. The optimized implementation achieves 392.173 MB/s, which is 50 times faster than the baseline implementation. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/GCCE50665.2020.9291973 | 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE) |
Keywords | DocType | ISSN |
AES-GCM,High-Level Synthesis,OpenCL,FPGA | Conference | 2378-8143 |
ISBN | Citations | PageRank |
978-1-7281-9803-3 | 0 | 0.34 |
References | Authors | |
2 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tsubasa Takaki | 1 | 0 | 0.34 |
| Yang Li | 2 | 165 | 13.44 |
| Kazuo Sakiyama | 3 | 583 | 57.35 |
| Shoei Nashimoto | 4 | 2 | 0.71 |
| Daisuke Suzuki | 5 | 306 | 21.80 |
| Takeshi Sugawara | 6 | 14 | 6.77 |