Name
Title | ||
|---|---|---|
Novel Fractional-N All Digital Frequency Locked Loop with Robustness for PVT variation |
Abstract | ||
|---|---|---|
This paper describes a novel Fractional-N all digital frequency locked loop (ADFLL) with robustness for PVT variation. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficient. The proposed ADFLL evaluated through the HSPICE simulation using 0.13 μm CMOS process. From simulation results, the proposed ADFLL has robustness for PVT variation, and the lock time is improved up to 57%. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ISMVL49045.2020.00-12 | 2020 IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL) |
Keywords | DocType | ISSN |
All Digital Frequency Locked Loop,Fractional-N,PVT variation,Lock Time | Conference | 0195-623X |
ISBN | Citations | PageRank |
978-1-7281-5407-7 | 0 | 0.34 |
References | Authors | |
0 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ryoichi Miyauchi | 1 | 0 | 0.34 |
| Akio Yoshida | 2 | 0 | 0.34 |
| Shuya Nakano | 3 | 0 | 0.34 |
| Hiroki Tamura | 4 | 72 | 21.29 |
| Koichi Tanno | 5 | 57 | 22.05 |
| Yutaka Fukuchi | 6 | 0 | 0.34 |
| Yukio Kawamura | 7 | 0 | 0.34 |
| Yuki Kodama | 8 | 0 | 0.34 |
| Yuichi Sekiya | 9 | 0 | 0.34 |