Paper Info
Title
Hardware Implementation for Belief Propagation Flip Decoding of Polar Codes
Abstract
Belief propagation (BP) decoding has natural advantages in throughput for polar codes to meet high-speed and low-latency requirements. The soft outputs of BP decoding can be utilized further for joint detection and decoding in the baseband communication system. However, its error-correction performance is not comparable with the successive cancellation list (SCL) decoding. Belief propagation flip (BPF) decoding is recently proposed to improve the error-correction performance of BP decoding and indicates the potential to compete with SCL decoding. In this paper, we propose an advanced BPF (A-BPF) scheme that reduces the decoding latency with the help of one critical bit and improves the error-correction performance by the proposed joint detection criterion. To improve area efficiency in the hardware level, an optimized sorting network is proposed and applied for the A-BPF decoder. The decoder is implemented on 65 nm CMOS technology for length-1024 and rate-1/2 polar codes, and the results show that the proposed decoder can achieve a close frame error rate performance to the SCL decoder with four lists and deliver a throughput of 5.17 Gb/s at E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> /N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> = 4.0 dB.
Year
DOI
Venue
2021
10.1109/TCSI.2020.3042597
IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
DocType
Volume
Polar codes,belief propagation (BP) decoding,bit-flipping,hardware implementation
Journal
68
Issue
ISSN
Citations 
3
1549-8328
1
PageRank 
References 
Authors
0.34
0
6
Name
Order
Citations
PageRank
Houren Ji171.86
Yifei Shen2155.36
Wenqing Song3153.35
Zaichen Zhang413420.67
xiaohu you52529272.49
Chuan Zhang610013.67