Paper Info
Title
The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications
Abstract
Tasks in modern embedded systems such as automotive and avionics communicate among each other using shared data towards achieving the desired functionality of the whole system. In commodity platforms, cores communicate data through the shared memory hierarchy and correctness is maintained by a cache coherence protocol. Recent works investigated the deployment of coherence protocols in real-time systems and showed significant performance improvements. Nonetheless, we find these works to suffer from two main drawbacks. 1) They suffer from significant latency delays due to coherence interference. 2) They require amendments to existing coherence protocols. This represents a significant obstruction hindering the industry adoption of these proposals since it requires to re-verify the coherence protocol. Coherence verification is considered one of the most complex challenges in computer architecture, which makes it inconceivable for chip manufacturers to adopt modifications to their already verified protocols that they have stable for decades.In this work, we propose PISCOT: a predictable and coherent bus architecture that (i) provides a considerably tighter bound compared to the state-of-the-art predictable coherent solutions (4× tighter bounds in a quad-core system). (ii) It does so with a negligible performance loss compared to conventional high-performance architecture coherence delays (less than 4% for SPLASH-3 benchmarks). This improves average performance by up to 5× (2.8× on average) compared to its predictable coherence counterpart. Finally, (iii) it achieves that without requiring any modifications to conventional coherence protocols.
Year
DOI
Venue
2020
10.1109/RTSS49844.2020.00029
2020 IEEE Real-Time Systems Symposium (RTSS)
Keywords
DocType
ISSN
embedded systems,shared data,shared memory hierarchy,cache coherence protocol,coherence protocols,coherence verification,verified protocols,predictable bus architecture,coherent bus architecture,quad-core system,high-performance architecture coherence delays,predictable coherent solutions,PISCOT,computer architecture
Conference
1052-8725
ISBN
Citations 
PageRank 
978-1-7281-8325-1
1
0.40
References 
Authors
0
2
Name
Order
Citations
PageRank
Salah Hessien110.40
Mohamed A. S. Hassan27919.44