Name
Title | ||
|---|---|---|
Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-<italic>N</italic> PLLs |
Abstract | ||
|---|---|---|
This paper describes all-digital enhancements for digital fractional-N phase-locked loops (PLLs) based on delta-sigma (ΔΣ) frequency-to-digital converters (FDCs). The enhancements include an improved dual-mode ring oscillator (DMRO)-based ΔΣ FDC architecture and a digital background calibration technique that compensates for the ΔΣ FDC's forward path gain error. The improved ΔΣ FDC has significantly relaxed timing constraints and a 3× smaller phase-frequency detector output pulse-width span relative to the prior art, which make it simpler to implement and amenable to higher-frequency reference signals. The calibration technique compensates for non-ideal DMRO frequencies in the digital domain. It eliminates the need to tune the DMRO instantaneous frequencies as a function of the PLL output frequency, thereby simplifying the DMRO implementation, and it also improves the phase noise performance of PLLs with high loop bandwidths. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TCSI.2020.3040346 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | DocType | Volume |
Delta-sigma (ΔΣ) modulation,digital background calibration,frequency-to-digital converter (FDC),frequency synthesizer,digital phase-locked loop (PLL) | Journal | 68 |
Issue | ISSN | Citations |
3 | 1549-8328 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Enrique Alvarez-Fontecilla | 1 | 2 | 2.41 |
| Amr I. Eissa | 2 | 0 | 0.68 |
| Eslam Helal | 3 | 0 | 0.68 |
| Colin Weltin-Wu | 4 | 0 | 0.34 |
| Ian Galton | 5 | 0 | 0.68 |