Name
Abstract | ||
|---|---|---|
Today's current standard in Cryptography is the symmetric Advanced Encryption Standard (AES) as selected by the US National Institute of Standards and Technology (NIST). It is also known as Rijndael Encryption Algorithm. With the emergence of high-performance cloud computing, it is important for the security encryption schemes to perform at higher speeds to provide fast, efficient, and secure data transmissions. The Rijndael S-box (substitution box) is the only non-linear component of the cryptosystem and significantly affects the overall performance of the AES encryption scheme. In this paper, we investigate various implementations for improving the hardware performance of the Rijndael S-box component of the AES algorithm in terms of delay and number of logic elements on the Altera Cyclone IV FPGA (Field programmable gate arrays) using the Intel Quartus II software and Verilog Hardware Description Language (Verilog HDL). |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ICDIS50059.2020.00009 | 2020 3rd International Conference on Data Intelligence and Security (ICDIS) |
Keywords | DocType | ISBN |
Cyber Security,Cryptography,Encryption,Advanced Encryption Standard (AES),FPGA,Altera Cyclone IV,Verilog HDL,Intel Quartus II,Rijndael Affine Field | Conference | 978-1-7281-9380-9 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Aaron Barrera | 1 | 0 | 0.34 |
| Chu-Wen Cheng | 2 | 0 | 0.34 |
| Sanjeev Kumar | 3 | 2727 | 139.04 |