Name
Abstract | ||
|---|---|---|
We propose a cost-effective approximate adder using a zero truncation technique with acceptable accuracy. The proposed adder design reduces the area by up to 23% compared to the approximate adders considered in this paper when implemented with a 32-nm CMOS technology. Furthermore, our adder shows 16%, 10%, 10%, and 16% better performance in area, power, power-delay product, and area-delay product, respectively, than the lower-part OR adder while providing an acceptable accuracy performance. To see the impact of approximation errors caused by our adder on real applications, it is adopted in a digital image processing and demonstrates that our adder rarely affects the output image quality. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ISOCC50952.2020.9332971 | 2020 International SoC Design Conference (ISOCC) |
Keywords | DocType | ISSN |
approximate adder,approximate computing,zero truncation,low power,energy efficiency | Conference | 2163-9612 |
ISBN | Citations | PageRank |
978-1-7281-8332-9 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jungwon Lee | 1 | 890 | 95.15 |
| Hyoju Seo | 2 | 0 | 1.35 |
| Yerin Kim | 3 | 0 | 0.34 |
| Yong Tae Kim | 4 | 22 | 8.62 |