Title
A 2.68mW/Gbps, 1.62-8.1Gb/s Receiver for Embedded DisplayPort Version1.4b to Support 14dB Channel Loss
Abstract
This paper proposes a low power wire-line receiver supporting embedded DisplayPort (eDP) 1.4b standard. The proposed receiver (Rx) operates with data rate of 1.62-8.1Gbps and supports 14dB channel loss at 8.1Gbps while meeting required Jitter Tolerance (JTOL) performance of bit error rate (BER) less than 10e-9 for TPS4 and PRBS7 data patterns. Implemented continuous-time linear equalizer (CTLE) supports edge based channel-equalization. Highly programmable analog front end (AFE) and clock data recovery (CDR) circuits guarantee operation across wide range of data rate while keeping the power consumption at optimum. The receiver supports 5000ppm down spread spectrum clocking (SSC) and 1500ppm frequency offset. Proposed receiver supports low power states and fast wakeup time in physical layer (PHY) to support Panel Self Refresh (PSR) and Self Refresh with Selective Update (PSR2) features of eDP standard. The test chip is fabricated in 10nm CMOS technology node and consists of 4 lanes and 1 PLL. Receiver consumes overall 2.68mW/Gbps/Lane at 8.1Gbps from 0.75V core supply and 1.2V of IO supply. Each lane is made shore line optimized with width of 135um and area of each lane of receiver is 0.12 mm2.
Year
DOI
Venue
2020
10.1109/A-SSCC48613.2020.9336149
2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Keywords
DocType
ISBN
PHY,eDP,DisplayPort,CDR,JTOL,Receiver,CTLE,PI,Low Power
Conference
978-1-7281-8437-1
Citations 
PageRank 
References 
0
0.34
0
Authors
17