Paper Info
Title
Energy and Area Efficient Mixed-Mode MCMC MIMO Detector
Abstract
A hybrid analog/digital signal processor has been proposed to implement energy-efficient multi-input-multi-output (MIMO) detectors. A sub-optimum MIMO detector based on Markov Chain Monte Carlo (MCMC) algorithm for a 4×4 MIMO system is presented. The main part of the required signal processing occurs in analog domain to reduce power consumption. The outputs of the proposed analog processor are converted to digital using a low-resolution analog-to-digital converter (ADC) in order to close the loop in digital domain. The proposed 4×4 MCMC MIMO detector is designed in a conventional 45 nm CMOS technology, that consumes 29.3 mW from 1.0 V supply. A throughput of 235.3 Mbps is achieved while operating at 1.0 GHz clock frequency. The design occupies 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon area.
Year
DOI
Venue
2020
10.1109/VLSI-SOC46417.2020.9344098
2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)
Keywords
DocType
ISSN
Optimum detector,Markov Chain Monte Carlo (MCMC),VLSI MIMO,Mixed-mode MIMO,Mixed-mode circuits
Conference
2324-8432
ISBN
Citations 
PageRank 
978-1-7281-5410-7
0
0.34
References 
Authors
0
3
Name
Order
Citations
PageRank
Amin Aghighi101.01
Behrouz Farhang-Boroujeny297284.30
Armin Tajalli335.51