Name
Abstract | ||
|---|---|---|
ABSTRACTHardware performance counters (HPCs) that measure low-level architectural and microarchitectural events provide dynamic contextual information about the state of the system. However, HPC measurements are error-prone due to non determinism (e.g., undercounting due to event multiplexing, or OS interrupt-handling behaviors). In this paper, we present BayesPerf, a system for quantifying uncertainty in HPC measurements by using a domain-driven Bayesian model that captures microarchitectural relationships between HPCs to jointly infer their values as probability distributions. We provide the design and implementation of an accelerator that allows for low-latency and low-power inference of the BayesPerf model for x86 and ppc64 CPUs. BayesPerf reduces the average error in HPC measurements from 40.1% to 7.6% when events are being multiplexed. The value of BayesPerf in real-time decision-making is illustrated with a simple example of scheduling of PCIe transfers. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1145/3445814.3446739 | ASPLOS |
DocType | ISSN | Citations |
Conference | Proceedings of the Twenty-Sixth International Conference on
Architectural Support for Programming Languages and Operating Systems (ASPLOS
21), 2021 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Subho S. Banerjee | 1 | 26 | 6.88 |
| Saurabh Jha | 2 | 9 | 2.94 |
| ?zg???ner | 3 | 33 | 18.65 |
| Ravishankar K. Iyer | 4 | 3489 | 504.32 |