Name
Abstract | ||
|---|---|---|
Continuous-time Δ Σ ADCs offer compact silicon area and low power consumption for various applications. The first two papers in this session present different techniques in continuous-time Δ Σ ADCs for audio applications and achieve impressive figures of merit. The third paper describes a new hybrid CT/DT loop architecture for a Δ Σ modulator without requiring any calibration or tuning. The fourth paper proposes a CT loop filter with DT noise shaping achieving $4^{{th }}$ -order noise shaping using a single OTA. The fifth paper introduces a pipelined ADC with a 1
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>
stage SAR and $2^{{nd }}$ stage $2 x$ -time-interleaved CT incremental Δ Σ ADC. The last two papers in this session describe techniques utilized to achieve high-linearity multi-GHz DACs. The sixth paper describes a 16GS/s DAC for software radio base stations. The last paper presents a 64GS/s DAC for BIST of RF sampling ADCs. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISSCC42613.2021.9366047 | 2021 IEEE International Solid- State Circuits Conference (ISSCC) |
DocType | Volume | ISSN |
Conference | 64 | 0193-6530 |
ISBN | Citations | PageRank |
978-1-7281-9550-6 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seyfi S. Bazarjani | 1 | 1 | 0.70 |
| Jong-Woo Lee | 2 | 0 | 1.69 |
| Marco Corsi | 3 | 19 | 3.61 |