Title
Error Floor Estimation of LDPC Coded Modulation Systems Using Importance Sampling
Abstract
One of the key weaknesses of low-density parity-check (LDPC) codes is the error floor that they typically exhibit at high signal-to-noise ratios (SNRs). Such an error floor is usually attributed to problematic structures known as trapping sets (TSs). The overwhelming majority of existing error floor estimation schemes consider the case of binary phase shift keying (BPSK) signalling. Unfortunately,...
Year
DOI
Venue
2021
10.1109/TCOMM.2021.3057625
IEEE Transactions on Communications
Keywords
DocType
Volume
Parity check codes,Modulation,Binary phase shift keying,Signal to noise ratio,Error analysis,Estimation,Quadrature amplitude modulation
Journal
69
Issue
ISSN
Citations 
5
0090-6778
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Peyman Neshaastegaran100.34
Amir H. Banihashemi249054.61
Ramy H. Gohary320128.76