Paper Info
Title
A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture
Abstract
This Ensuing generation of FPGA circuit tolerates the combination of lot of hard and soft cores as well as devoted accelerators on a chip. The Heterogene Multi-Processor System-on-Chip (Ht-MPSoC) architecture accomplishes the requirement of modern applications. A compound System on Chip (SoC) system designed for single FPGA chip, and that considered for the performance/power consumption ratio. In the existing method, a FPGA based Mixed Integer Programming (MIP) model used to define the Ht-MPSoC configuration by taking into consideration the sharing hardware accelerator between the cores. However, here, the sharing method differs from one processor to another based on FPGA architecture. Hence, high number of hardware resources on a single FPGA chip with low latency and power targeted. For this reason, a fuzzy based MIP and Graph theory based Traffic Estimator (GTE) are proposed system used to define New asymmetric multiprocessor heterogene framework on microprocessor (AHt-MPSoC) architecture. The bandwidths, energy consumption, wait and transmission range are better accomplished in this suggested technique than the standard technique and it is also implemented with a multi-task framework. The new Fuzzy control-based AHt-MPSoC analysis proves significant improvement of 14.7 percent in available bandwidth and 89.8 percent of energy minimized to various traffic scenarios as compared to conventional method.
Year
DOI
Venue
2022
10.3233/JIFS-189737
JOURNAL OF INTELLIGENT & FUZZY SYSTEMS
Keywords
DocType
Volume
FPGA, MPSoC, hardware accelerators, MIP model, fuzzy control, GTE
Journal
42
Issue
ISSN
Citations 
2
1064-1246
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Arun Prasath Raveendran100.34
Jafar A. Alzubi201.01
Ramesh Sekaran341.74
R. Manikandan4218.15