Name
Title | ||
|---|---|---|
Understanding Insecurity of Processor Caches Due to Cache Timing-Based Vulnerabilities |
Abstract | ||
|---|---|---|
This article discusses a recently developed test suite for checking timingbased vulnerabilities in processor caches, which has revealed the insecurity of today's processor caches. The susceptibility of caches to these vulnerabilities calls for more research on secure processor caches. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/MSEC.2021.3055799 | IEEE Security & Privacy |
Keywords | DocType | Volume |
Timing,Security,Probes,Coherence,Data models,Table lookup,Software | Journal | 19 |
Issue | ISSN | Citations |
3 | 1540-7993 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shuwen Deng | 1 | 4 | 1.77 |
| Wenjie Xiong | 2 | 29 | 9.94 |
| Jakub Szefer | 3 | 398 | 37.00 |