Name
Title | ||
|---|---|---|
Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network |
Abstract | ||
|---|---|---|
Three-dimensional (3D) FPGAs can implement much higher logic density than present 2D FPGAs by stacking multiple FPGA device layers with 3D IC technology. However, routing architectures of 3D FPGAs are very different from those of conventional FPGAs with a regular 2D array structure, so a new universal architecture-aware placement method is required. In this work, we propose a convolutional neural network (CNN)-based pre-routing wirelength prediction cost function for 3D FPGA placement. By training an optimized CNN with a dataset made from actual routing results, the CNN can learn 3D FPGA architecture features and predict net wirelength accurately. Dataset generation, CNN structure exploration, and training processes are universal and automated, so the proposed method can be easily applied to different 3D FPGAs. The evaluation results show that post-routing total wirelength can be significantly reduced with a 3D FPGA placer that uses the CNN-based cost function for global placement phase and then uses the conventional half-perimeter wirelength (HPWL)-based cost function for detailed placement phase. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/CANDAR51075.2020.00040 | 2020 Eighth International Symposium on Computing and Networking (CANDAR) |
Keywords | DocType | ISSN |
3D FPGA, Placement | Conference | 2379-1888 |
ISBN | Citations | PageRank |
978-1-7281-8222-3 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Qian Zhao | 1 | 0 | 0.34 |
| Motoki Amagasaki | 2 | 0 | 0.68 |
| Masahiro Iida | 3 | 0 | 1.01 |
| Takaichi Yoshida | 4 | 0 | 0.68 |